Design Considerations of a Multiple Inner Product and Accumulate Vector Functional Unit

A large number of scientific applications require computations that involve operations on sparse matrices. Due to irregularities induced by the diverse sparsity patterns, many operations on sparse matrices execute inefficiently on traditional scalar and vector architectures. In order to tackle this issue a scheme has been proposed [1] that alleviates the sparse matrix storage and computation overhead on vector processors. The scheme introduces a new sparse matrix storage format and utilizes the Multiple Inner Product and Accumulate (MIPA) vector pipelined functional unit to perform the sparse matrix vector multiplication, the function that constitutes the core operation of most sparse matrix applications. The implementation of the MIPA functional unit poses a number of challenges and its design considerations will be the focus of this work. The MIPA unit operates on a vector containing the nonzero elements of a sparse matrix with the associated positional information and a multiplicand vector in order to produce a vector containing a number of inner products. The vector of nonzero elements, as defined by the scheme in [1], represents a number of partial rows of the sparse matrix. Therefore, the processing of the vector produces multiple data streams within the MIPA unit that correspond to the multiplicity of rows it represents. This fact, combined with the necessity to feed back data over a multi-stage floating point adder to perform the accumulation, results in a scheduling problem. In this paper we propose a MIPA functional unit design that addresses this issue in an efficient manner. Simulation results on a sparse matrix benchmark suit suggest that by using our proposed scheduling scheme utilizing a multiple pipeline implementation of the functional unit we can achieve a near optimal resource utilization. Keywords— vector processing, sparse matrices, matrix vector multiplication